1.• High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications
高性能汽车级微控制器，用于与安全密切相关的应用
– Dual CPUs Running in Lockstep
运行步伐一致的双CPU
– ECC on Flash and RAM Interfaces
对闪存及随机存储器接口进行错误检查及纠正
– Built-In Self-Test (BIST) for CPU and On-chip RAMs
内置中央处理器及片上只读存储器自测功能（BIST）
– Error Signaling Module With Error Pin
带有错误引脚的错误信号传送模块，
– Voltage and Clock Monitoring
电压及时钟监控
• ARM® Cortex®-R4F 32-Bit RISC CPU
ARM® Cortex®-R4F，32位精简指令集中央处理器
– 1.66 DMIPS/MHz With 8-Stage Pipeline
运算速度为166万条指令每秒/兆赫兹，8通道
– FPU With Single- and Double-Precision
浮点运算单元，包含单精度和双精度
– 12-Region Memory Protection Unit (MPU)
12个区域存储器保护单元（MPU）
– Open Architecture With Third-Party Support
开放的架构，由第三方支持
• Operating Conditions
运行条件
– Up to 180-MHz System Clock
系统时钟频率最高可达180兆赫兹
– Core Supply Voltage (VCC): 1.14 to 1.32 V
芯片供电电压（VCC）为：1.14 到1.32 V
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
输入/输出供电电压(VCCIO)为：3.0 到3.6 V
Packages
封装
– 144-Pin Quad Flatpack (PGE) [Green]
四边形平版封装，144个引脚（PGE）[绿色]
– 337-Ball Grid Array (ZWT) [Green]
网格阵列封装，337个球形引脚（ZWT）[绿色]
2.Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW.
当输出缓冲器将输出驱动到一个较低的电压水平时，如果输出电压低于VREFLOW,那么输出缓冲器的阻抗将增加到高阻状态。在使用容性负载或者任何无电流流过（例如，当一条接地电阻路径的电压被缓冲器驱动为低水平时）的负载时，内部接地母线与输出引脚之间将发生高度解耦。缓冲器上用于拉高输出电压（使其高于 VREFLOW）的电流负载将与缓冲器的输出阻抗成反比，可以确保输出电压小于或等于VREFLOW。